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VerificationArchitected for the AI era.

The harness between your verification flow and any AI model. Structure instead of prompting, so an LLM works with far less context.

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A harness, not a prompt.

VerifArch is the harness built for verification. It gives an LLM deterministic tools to navigate the RTL, the testbench, the waveforms, the coverage and the register map, under strict guidelines, in a sandboxed environment. The model no longer reads thousands of lines to change one function. It asks, gets the exact answer, and acts.

Block diagram Two inputs: your AI model, hosted or local, and your in-house simulation flow, as it is. They feed VerifArch, inside which the model navigates the spec, design, bench, runs, waves and coverage. The output is your IP, verified: complete, structured, evidence-backed. Your AI model hosted or local Your simulation flow in-house, as it is VerifArch The harness for verification Spec Spec Design Design Bench Bench Runs Runs Waves Waves Coverage Coverage Your IP, verified complete, structured, evidence-backed Block diagram Two inputs: your AI model, hosted or local, and your in-house simulation flow, as it is. They feed VerifArch, inside which the model navigates the spec, design, bench, runs, waves and coverage. The output is your IP, verified: complete, structured, evidence-backed. Your AI model hosted or local Simulation flow yours, as it is VerifArch The harness for verification Spec Spec Design Design Bench Bench Runs Runs Waves Waves Coverage Coverage Your IP, verified complete, structured, evidence-backed

Point at a lane inside VerifArch to see where it is used in the flow below.

  • Deterministic tools

    • What drives this signal.
    • What sits at this address.
    • Which bins are unhit.
    • Every answer comes from the design and the data, bounded to fit the model's context.
    • Never a guess.

  • Strict guidelines

    • Work moves in gated stages: compile, simulate, audit, evidence.
    • One bounded task at a time, wrapped in checks on both sides.
    • Nothing advances on a claim.

  • Sandboxed

    • Each step runs in a filesystem and network jail derived from what it is meant to do.
    • Your RTL stays read-only.
    • Any model, hosted or local.

One flow, the way a block really gets verified

From the spec to signoff evidence, each stage bounded, gated and traceable to a requirement.

  1. Verification planning and requirements tracking

    The spec becomes requirements, and a requirement is proven by goals: a covergroup, a check, an assertion, or a review. The plan tracks each one from unmapped to mapped to verified, with coverage read from the simulator as the truth, never stored, and it always knows what is next.

    spec.pdf4.2 Transfer completion4.2 Transfer completionREQUIREMENTSgoal · statusREQ-041done on the last beatcovergroupverifiedREQ-042abort mid-transfercheckmappedREQ-043illegal length rejectedassertionnextcoverage is the truth

  2. Testbench bringup

    Two ways in, one result: a bench the LLM can navigate without reading all of it.

    • Existing bench

      Indexed as it is: classes, inheritance, topology, covergroups, conventions. The LLM asks for one class or one method at a time and works inside your style.

    • New bench

      From the interfaces and the intent, a complete UVM testbench tree is generated, ready to compile, and brought up gated on the base test running clean.

    testbenchexisting · newEXISTING BENCH · INDEXEDenv/indexedagents/indexedsequences/indexedcheckers/indexedtests/indexedtopology, inheritance, covergroupsread from source, not simulatedyour conventions keptNEW BENCH · GENERATEDdut_env.svdut_agent.svdut_seq_lib.svdut_scoreboard.svdut_tb_top.svagents, environment, scoreboard,coverage, clocks and reset wiredbase test compiles and runs clean

  3. Implementation flow

    Each requirement becomes one bounded task: a test, a covergroup, a check or an assertion. The LLM builds what the requirement mandates, consulting the project's knowledge base, the documents you give it, before and while it writes. The result must compile, simulate, pass audit and produce evidence a reviewer can check before the plan advances. The gate decides done, not the model.

    REQ-042 · developone task, gatedcheck_abort_mid_transfer.svPROJECTKNOWLEDGE BASEspec §4.2register mapinterface protocolbench guidelinesdocuments you give itGATEScompilebase testauditplan advancesnothing advances on a claim

  4. Root cause analysis

    A failing check or assertion is root-caused once, across every test it fails in: logs, waveforms, RTL and spec. The cause is classified as design, bench or uncertain, with the evidence cited, and the design is never silently absolved. A fix lands against a report, not a hunch.

    waves · dma_short_transfer0 ns – 160 nsclkvalidreadydonehereROOT CAUSE · DUTacross every failing testdone asserted one beat before the last transferevidence cited: log, wave, rtl, spec §4.2

  5. Coverage analysis and closure

    Coverage is read as it is, from your simulator's own database: summary, covergroups, bins, toggle and branch gaps. Every unhit hole gets a reason and a typed recommendation: extend a test, add one, change a constraint, rework the covergroup, or mark it unreachable. You decide. Nothing launders the percentage.

    coverage · cg_transferfunctionallen[1]unhitlen[2..4]hitlen[max]hitabort × lenpartialWHY UNHIT · len[1]no sequence constrains len to 1; the default range starts at 2recommendation: a targeted sequence, then re-runyou decide; no automatic waivers

What stays yours

VerifArch sits between your flow and the model. It replaces neither.

  • Simulator and flow

    Yours. VerifArch registers your existing compile and simulation flow and reads what it produces: logs, waveforms, coverage. Nothing is replaced.

  • AI model

    Any. A hosted model, or a local one on your own hardware. You choose the provider, and you can change it later.

  • Sources and results

    Stay in your environment. VerifArch runs where your flow runs. What a model is shown is your decision.

See it in action

Request access to the demo and explore it at your own pace. If you want to go deeper, book a call with the people building VerifArch. Tell us about your flow and your main bottleneck; we read every request ourselves.

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